1. Field of the Invention
The present invention relates generally to stereolithography and, more specifically, to the use of stereolithography in the manufacture of electronic components. More particularly, the invention pertains to a method for sealing and protecting an interface area between a semiconductor device and a carrier substrate to which it is attached and, optionally, encapsulation of at least part of the assembly.
2. State of the Art
Flip-chip style packaging for semiconductor dice is becoming ever more popular. In a flip-chip package, an array or pattern of external conductive elements such as solder bumps or conductive or conductor-filled epoxy pillars protrude from the active surface of the semiconductor die for use in mechanically and electrically connecting the semiconductor die to like-patterned ends of conductive traces of higher level packaging such as a carrier substrate.
There is typically a large mismatch in the coefficient of thermal expansion (CTE) between the material of the semiconductor die and that of the carrier substrate, such as a circuit board or interposer, bearing the conductive traces to which the external conductive elements of the die are bonded. Thus, significant lateral stresses between the semiconductor die and carrier substrate result from normal thermal cycling. Without a strong mechanical attachment of the semiconductor die to the substrate, the die might pop loose from the carrier substrate, or one or more of the external conductive elements might fracture or release from its corresponding conductive trace. In addition, the small spacing or pitch of the external conductive elements creates a significant potential for shorting between adjacent conductive elements or conductive elements and adjacent carrier substrate traces due to the presence of a dust particle or condensed moisture between the semiconductor die and the carrier substrate. Therefore, when a flip-chip type of electronic device, such as a semiconductor die, is conductively attached to a carrier substrate, underfilling the space between the device and substrate with an electrically insulative material is very desirable to enhance the mechanical bond between the die and the substrate and to mutually laterally dielectrically isolate adjacent electrical connections between the die and the carrier substrate.
The continuing trend toward smaller semiconductor dice having smaller, more densely packed external conductive elements, and dice attached to substrates at an ever increased packing density, all exacerbate the problems already noted and further increase the desirability of using an insulating underfill.
As depicted in FIG. 1, an exemplary, conventional underfill structure 38 is formed between a flip-chip style semiconductor die 20 and a carrier substrate 10. The semiconductor die 20 has an active surface 22 with a plurality of conductive pads 32 to which external conductive elements 30 are bonded or on which external conductive elements 30 are formed, all as known in the art. In this illustration, the external conductive elements 30 comprise an array of solder balls. The semiconductor die 20 is connected electrically to the carrier substrate 10 by facing the active surface 22 to the carrier substrate face 12 and reflow-bonding the external conductive elements 30 to conductive trace pads 14 on the carrier substrate face 12.
Conventional polymeric materials used to form a dielectric underfill structure 38 are relatively viscous, many times the viscosity of water, and complete underfilling of the area between a semiconductor die 20 and a carrier substrate 10 is thus difficult to achieve. Often, these polymeric materials must be heated to an undesirably high temperature before they will flow in a satisfactory manner. The problem is especially acute where the device-substrate spacing is small. Thus, prior art methods use a vacuum source to attempt to draw the underfill material into the interstitial volume or spaces 34 surrounding the external conductive elements 30, i.e., balls, bumps, columns, etc.
As shown in FIG. 1, adequate removal of air, water vapor and condensed moisture from the interstitial volume or spaces 34, particularly the crevices 36 at connector interfaces with the active surface 22 and carrier substrate 10, is not consistently achieved. Voids or bubbles 26 of gas or condensed, liquid water may remain in the underfill structure 38 in the interstitial volume or spaces 34 and may conductively join external conductive elements 30, plurality of conductive pads 32 and conductive trace pads 14 to provide a short circuit. Moreover, the material of the underfill structure 38 does not adhere to all of the surfaces of semiconductor die 20 and carrier substrate 10 in the interconnection area under the “footprint” of the die, thus lessening the mechanical bond strength therebetween. Furthermore, the so-called Fine Ball Grid Array (FBGA) now in use in the semiconductor industry, using very small-dimensioned balls and ball pitch, as well as typically a reduced spacing between adjacent semiconductor dice on a carrier substrate and the disposition of dice on both sides of a carrier substrate, limits the use of vacuum apparatus to enhance the effective underfill between dice and the carrier substrate. As a result, the manufacture of such electronic assemblies results in high cost and a relatively high reject and rework rate, which is obviously very costly.
In the past decade, a manufacturing technique termed “stereolithography,” also known as “layered manufacturing,” has evolved to a degree where it is employed in many industries.
Essentially, stereolithography (STL) as conventionally practiced, involves utilizing a computer to generate a three-dimensional (3-D) mathematical simulation or model of an object to be fabricated, such generation can usually be effected with 3-D computer-aided design (CAD) software. The model or simulation is mathematically separated or “sliced” into a large number of relatively thin, parallel, usually vertically superimposed layers, each layer having defined boundaries and other features associated with the model (and thus the actual object to be fabricated) at the level of that layer within the exterior boundaries of the object. A complete assembly or stack of all of the layers defines the entire object, and surface resolution of the object is, in part, dependent upon the thickness of the layers.
The mathematical simulation or model is then employed to generate an actual object by building the object, layer by superimposed layer. A wide variety of approaches to stereolithography by different companies has resulted in techniques for fabrication of objects from both metallic and nonmetallic materials. Regardless of the material employed to fabricate an object, stereolithographic techniques usually involve disposition of a layer of unconsolidated or unfixed material corresponding to each layer within the object boundaries, followed by selective consolidation or fixation of the material to at least a semisolid state in those areas of a given layer corresponding to portions of the object, the consolidated or fixed material also at that time being substantially concurrently bonded to a lower layer. The unconsolidated material employed to build an object may be supplied in particulate or liquid form, and the material itself may be consolidated or fixed or a separate binder material may be employed to bond material particles to one another and to those of a previously formed layer. In some instances, thin sheets of material may be superimposed to build an object, each sheet being fixed to a next lower sheet and unwanted portions of each sheet removed, a stack of such sheets defining the completed object. When particulate materials are employed, resolution of object surfaces is highly dependent upon particle size, whereas when a liquid is employed, surface resolution is highly dependent upon the minimum surface area of the liquid which can be fixed and the minimum thickness of a layer which can be generated. Of course, in either case, resolution and accuracy of object reproduction from the CAD file is also dependent upon the ability of the apparatus used to fix the material to precisely track the mathematical instructions indicating solid areas and boundaries for each layer of material. Toward that end, and depending upon the layer being fixed, various fixation approaches have been employed, including particle bombardment (electron beams), disposing a binder or other fixative (such as by ink-jet printing techniques), or irradiation using heat or specific wavelength ranges.
An early application of stereolithography was to enable rapid fabrication of molds and prototypes of objects from CAD files. Thus, either male or female forms on which mold material might be disposed might be rapidly generated. Prototypes of objects might be built to verify the accuracy of the CAD file defining the object and to detect any design deficiencies and possible fabrication problems before a design was committed to large-scale production.
In more recent years, stereolithography has been employed to develop and refine object designs in relatively inexpensive materials and has also been used to fabricate small quantities of objects where the cost of conventional fabrication techniques is prohibitive for same, such as in the case of plastic objects conventionally formed by injection molding. It is also known to employ stereolithography in the custom fabrication of products generally built in small quantities or where a product design is rendered only once. Finally, it has been appreciated in some industries that stereolithography provides a capability to fabricate products, such as those including closed interior chambers or convoluted passageways, which cannot be fabricated satisfactorily using conventional manufacturing techniques. It has also been recognized in some industries that a stereolithographic object or component may be formed or built around another, pre-existing object or component to create a larger product.
However, to the inventor's knowledge, stereolithography has yet to be applied to mass production of articles in volumes of thousands or millions, or employed to produce, augment, or enhance products including flip-chip semiconductor devices in large quantities, where minute component sizes are involved, and where extremely high resolution and a high degree of reproducibility of results is required. Furthermore, stereolithography methods have not been used to package, at the wafer level, large numbers of flip-chip dice of the same or differing configurations to provide underfilled or even packaged devices that become environmentally sealed upon bonding to a carrier substrate, such as a printed circuit board (PCB). In such a method, the difficulties of precisely locating a number of pre-existing components for stereolithographic application of material thereto without the use of mechanical alignment techniques is required to assure precise, repeatable placement of encapsulant material.